-40%
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer

National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer

$ 26.37

Availability: 100 in stock
  • Type: Link adapter
  • MPN: DS90C124C
  • Restocking Fee: No
  • Return shipping will be paid by: Buyer
  • All returns accepted: Returns Accepted
  • Item must be returned within: 14 Days
  • Refund will be given as: Money Back
  • Country/Region of Manufacture: USA
  • Condition: New – Open box
  • Brand: National Semiconductor

    Description

    National Semiconductor OVTFPD DS90C124C and DS90C241 Serializer and Deserializer
    This is a Brand New National Semiconductor National Semiconductor OVTFPD DS90C124C and DS90C241
    --Description
    The DS90C241/124 Chipset translates a 24-bit parallel businto a fully transparent data/control LVDS serial stream withembedded clock information. This single serial stream sim-plifies transferring a 24-bit bus over PCB traces and cable byeliminating  the  skew  problems  between  parallel  data  andclock paths. It saves system cost by narrowing data pathsthat in turn reduce PCB layers, cable width, and connectorsize and pins.The  DS90C241/124  incorporates  LVDS  signaling  on  thehigh-speed I/O. LVDS provides a low power and low noiseenvironment for reliably transferring data over a serial trans-mission path. By optimizing the serializer output edge ratefor the operating frequency range EMI is further reduced.In addition the device features pre-emphasis to boost signalsover  longer  distances  using  lossy  cables.  Internal  DC  bal-anced  encoding/decoding  is  used  to  support  AC-Coupledinterconnects
    --Product Attributes
    5 MHz–35 MHz clock embedded and DC-Balancing24:1 and 1:24 data transmissionsn
    User defined Pre-Emphasis driving ability throughexternal resistor on LVDS outputs and capable to driveup to 10 meters shielded twisted-pair cablen
    User selectable clock edge for parallel data on bothTransmitter and Receivern
    Internal DC Balancing encode/decode – SupportsAC-coupling interface with no external coding requiredn
    Individual power-down controls for both Transmitter andReceivern
    Embedded clock CDR (clock and data recovery) onReceiver and no external source of reference clockneededn
    All codes RDL (random data lock) to supporthot-pluggable applicationsn
    LOCK output flag to ensure data integrity at Receiversiden
    Balanced TSETUP/THOLDbetween RCLK and RDATA onReceiver siden
    PTO (progressive turn-on) LVCMOS outputs to reduce
    EMI and minimize SSO effectsn
    All LVCMOS inputs and control pins have internal pulldownn
    On-chip filters for PLLs on Transmitter and Receivern48-pin TQFP packagen
    Pure CMOS .35 µm processn
    Power supply range 3.3V±10%n
    Temperature range –40 °C to +105 °C
    8 kV HBM ESD structure
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